Red Semiconductor debuts Ordo1 VISC-based accelerator core for RISC-V

Ordo1 targets low-power, real-time AI with VISC

October 23, 2025

David Harold

UK startup Red launches Ordo1, an AI/flow-control accelerator IP block for RISC-V. The company is partnering with Aion for test silicon, and with Codasip to integrate Red’s VISC IP into Codasip’s RISC-V cores. The company has joined RISC-V International and closed a seven-figure Seed+ round supplemented by EU grants. Claims include up to 5× speedups on matrix-heavy workloads and >90% power reduction versus “baseline” RISC-V, plus a smaller codebase and compact area add-on. Red CEO James Lewis (Source: Red Semiconductor) Red Semiconductor has announced Ordo1, an accelerator IP core built on the company’s VISC architecture designed to bolt onto RISC-V

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Red Semiconductor debuts Ordo1 VISC-based accelerator core for RISC-V

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