Researchers from several US universities teamed up with SkyWater Technology to build a new kind of computer chip that stacks memory and computing vertically instead of spreading them flat. By shortening the distance data has to travel, the chip runs AI workloads faster and more efficiently. Built in a US commercial foundry, the prototype shows that advanced 3D chip designs can move from the lab into domestic manufacturing, pointing toward more capable and energy-efficient AI hardware.
Engineers from Stanford University, Carnegie Mellon University, the University of Pennsylvania, and the Massachusetts Institute of Technology have worked with SkyWater Technology, a US-based pure-play semiconductor foundry, to develop a multi-layer computer chip based on monolithic three-dimensional integration. The prototype demonstrates a manufacturing approach and system architecture intended to address long-standing limitations in data movement, memory access, and domestic chip fabrication for AI workloads.
Conventional processors rely largely on two-dimensional layouts in which logic and memory are distributed across a single plane. In such designs, data must travel laterally across relatively long interconnects, which constrains performance as computing elements outpace memory access. This imbalance, often described as the memory wall, has increasingly limited the gains from faster logic. For many years, semiconductor progress mitigated this constraint by shrinking transistors and increasing density, but that strategy now faces physical and economic limits to further miniaturization.
The new chip architecture departs from planar layouts by vertically integrating memory and logic across multiple ultra-thin layers, fabricated sequentially in a single process flow. Dense vertical interconnects link these layers, enabling high-bandwidth communication over short distances. Rather than stacking separately manufactured dies, the team used a monolithic approach in which each tier is built directly on top of the previous one at temperatures low enough to preserve existing circuitry. This method allows substantially finer vertical connectivity than die-stacking techniques and reduces interlayer communication overhead.
Hardware measurements and simulations indicate that this vertical integration improves performance and efficiency by reducing data movement latency and energy. Initial silicon prototypes fabricated at SkyWater show severalfold gains compared with comparable two-dimensional chips, while simulations of designs with additional layers indicate larger improvements on representative AI workloads, including those derived from transformer-based models. These gains arise from closer proximity between memory and compute units and from the increased number of parallel data paths enabled by vertical wiring.
The researchers emphasize that fabrication in a commercial US foundry represents an important aspect of the work. Prior demonstrations of monolithic 3D integration largely remained within academic cleanrooms, limiting their relevance to scalable manufacturing. Producing the prototype in a domestic foundry demonstrates compatibility with industrial processes and suggests a path toward broader adoption within the US semiconductor ecosystem. This capability aligns with efforts to strengthen domestic manufacturing and reduce dependence on offshore advanced fabrication.
Beyond raw performance, the design targets improvements in energy-delay product, a metric that captures the trade-off between speed and energy consumption. By shortening interconnect lengths and increasing bandwidth density, the architecture reduces the energy required to move data while maintaining high throughput. The researchers argue that such gains are necessary for future AI systems, which increasingly derive their cost and power consumption from data movement rather than arithmetic operations.
The work also highlights implications for workforce development and research infrastructure. Transitioning from planar to vertically integrated chips requires new design methodologies, tools, and fabrication expertise. Through academic–industry collaborations and programs such as the Microelectronics Commons California-Pacific-Northwest AI Hardware Hub, students and researchers are gaining experience with monolithic 3D integration techniques. The team views this effort as part of a broader shift toward vertically integrated architectures that can be designed and manufactured domestically, supporting continued innovation in AI hardware within the United States. More information can be found here.
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