TSMC’s 20-angstrom process kicks off the sub-atomic era+

If Moore’s Law is dead, someone forgot to tell TSMC

Posted: By Jon Peddie 06.20.22
Source ASML


At TSMC’s annual North America technology symposium, the company revealed its roadmap which showed its next-generation N2 process due in 2025 would use nanosheet transistors. That will be possible says the world's biggest, and currently most advanced semiconductor fab,  because in 2024 it is getting ASML’s high-NA EUV advanced chipmaking tool. The machine is the size of a double-decker bus and costs $400-million each

TSMC’s Y.J. Mii, senior vice president of research & development, said the N2 (20 Å) process will be able to offer a 10-15% speed improvement at the same power over N3, or 25-30% power reduction at the same speed—which sounds an awful lot like Moore’s Law.

TSMC showed its roadmap for all its processes and disclosed its N3 technology will include the TSMC Finflex architectural that the company says offers unparalleled flexibility for designers. Finflex offers choices of different standard cells with a 3-2 fin configuration for ultra-performance, a 2-1 fin configuration for power efficiency and transistor density, and a 2-2 fin configuration providing a balance between the two.

TSMC showed two customer applications of its -SoIC chip stacking capability: an intelligence processing unit stacked on top of a deep trench capacitor die using wafer-on-wafer (WoW) technology, and a SoIC-based CPU using its chip-on-wafer (CoW) technology that can stack SRAM as a Level 3 cache.

TSMC said with N7 chips in production for both CoW and WoW, support for N5 technology is scheduled for 2023 (see roadmap below). And the company plans to have the world's first fully automated 3DFabric factory is set to begin production in the second half of 2022 for SoIC and other devices.

TSMC advanced process roadmap (Source TSMC)


TSMC said it is developing an N6e node to provide compute power and energy efficiency for edge AI and IoT devices. N6e will be using TSMC's 7nm process and the company said it should provide three times greater logic density than N12e. It will be part of TSMC's ultra-low-power platform, which includes logic, RF, analog, embedded nonvolatile memory, and power management IC libraries for applications in edge AI and the IoT.

What do we think?

We will soon be at the truly sub-atomic level in semiconductor fabrication—something that was predicted as unobtainable just a few years ago when the industry was building 20 and 14 nm parts. Now we are moving toward the production of 20-angstrom transistors that even a scanning tunneling microscope may be challenged by a STM offers a good lateral resolution of one angstrom) Silicon’s atomic size is about two angstroms (2×10-10 m). If these barriers can be broken, and those in the industry are optimistic they can, we will soon be referring to transistors that are measured in femtometers, 10-15 m. Of course, this is all make-believe because we can’t see it prove that the transistors are really there—we just believe they are and therefore they are.

 “It’s there, can’t you see it,” says the engineer in the middle (Image source TSMC)