Intel decouples backplane power from its RibbonFET transistors

Claims to be the first to make it work.

Jon Peddie

Intel has announced a pioneering implementation of backside power delivery, called PowerVia, on a test chip. This advancement addresses interconnect bottlenecks and will be integrated into the Intel 20A process node in early 2024. PowerVia enables power routing to the backside of a wafer, improving chip performance. Intel dedicated separate development efforts to ensure its seamless integration into the 20A and 18A process nodes. The technology demonstrated high cell utilization and significant transistor scaling, empowering chip designers to achieve performance and efficiency gains. The test chip also showcased improved voltage droop and frequency. Overall, PowerVia offers a solution to interconnect

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