Ambiq Micro recently shared a closer look at its upcoming SoC design aimed squarely at ultra-low-power edge AI devices. Built on a new 12 nm SPOT platform using TSMC’s N12e FinFET process, the chip introduces an Ultra-Low-Power mode that can run at just 300 mV. That tiny voltage still supports meaningful AI inference thanks to the Arm Ethos-U85 NPU. Behind the scenes, Ambiq redesigned the chip’s power management and foundation IP to make such low-voltage operation practical. The company plans first Atomiq110 samples before targeting production in 2027.
Ambiq Micro disclosed new technical details of its upcoming Atomiq sSoC AI processor designed for ultra-low-power edge computing and AI inference. The device uses Ambiq’s newly developed 12-nanometer SPOT (Sub-threshold Power Optimized Technology) platform implemented on the TSMC N12e FinFET process. The architecture introduces a new Ultra-Low-Power operating mode that functions at voltages as low as 300 millivolts, the lowest voltage level ever achieved in Ambiq’s product line. Ambiq plans initial samples of the Atomiq110 device ahead of a production target in 2027.
The Atomiq design combines the company’s subthreshold circuit methodology with a FinFET manufacturing node. Earlier generations of ultra-low-power silicon relied primarily on planar CMOS processes to operate in near-threshold regimes. Ambiq adapted its SPOT architecture to the N12e FinFET process to extend sub- and near-threshold operation to higher-performance levels. The design expands voltage scaling across three operating regimes: Ultra-Low-Power (ULP), Low-Power (LP), and High-Performance (HP). The new ULP mode targets operation around 300 mV while preserving useful computational throughput.
The processor targets edge AI workloads that benefit from parallel execution rather than extremely high clock frequencies. The device integrates the previously announced Arm Ethos-U85 neural processing unit. This NPU performs large numbers of multiply-accumulate operations in parallel and delivers tens of billions of operations per second even at relatively modest clock speeds. The architecture allows inference workloads to run in ULP mode at frequencies near 100 MHz while maintaining substantial computational output.
Ambiq redesigned the power management architecture in order to enable stable operation at extremely low voltages. The chip integrates a configurable multi-channel Single-Inductor Multiple-Output buck converter that distributes power across several voltage rails. The control logic adjusts voltage levels dynamically in response to workload demand, temperature conditions, and manufacturing variations. The system supports current loads that range from nanoamp levels during idle states to milliamp levels under heavier processing activity.
Figure 1. Ambiq’s SPOT platform. (Source: Ambiq)
Ambiq also created new foundation intellectual property blocks that support reliable operation at ultra-low voltages. Engineers validated the 12 nm SPOT platform on silicon within Ambiq Laboratories, establishing a key milestone toward the commercial deployment of the Atomiq architecture.
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