Memory has become one of the defining constraints in modern computing. AI workloads, high-speed networking, radar, imaging, and physical AI systems all require more capacity and bandwidth, yet designers face shrinking form factors, supply constraints, and longer product lifecycle requirements. AMD’s new Versal Premium Gen 2 Memory on Package (MoP) devices address those challenges by integrating LPDDR5X memory directly into the adaptive SoC package. The result combines higher memory density, reduced board complexity, and long-term availability in a platform aimed at embedded, industrial, communications, aerospace, and defense applications.
(Source: AMD)
Memory has emerged as one of the most valuable resources in computing. Every major technology transition has increased memory requirements. The PC era drove demand for local DRAM. The Internet expanded memory footprints in servers and networking equipment. Cloud computing increased data movement and storage requirements. AI now pushes memory consumption at a pace that exceeds historical trends. AMD believes embedded and adaptive computing customers face a unique challenge as this transition unfolds.
The company argues that AI demand has created supply constraints, increased costs, and concentrated memory sourcing among a small number of suppliers. Those conditions affect embedded, industrial, communications, aerospace, and defense customers that require long product lifecycles and stable supply chains. Data center memory technologies solve bandwidth challenges, yet they often fail to align with the operational realities of embedded deployments.
AMD’s answer comes in the form of the Versal Premium Gen 2 Memory on Package adaptive SoC. The device integrates up to 32 GB of LPDDR5X memory directly into the package and delivers up to 288 GB/s of memory bandwidth. AMD couples that memory subsystem with the existing Versal Premium Gen 2 architecture, which includes programmable logic, Arm processing subsystems, DSP engines, PCIe Gen6, CXL 3.1, 128G SerDes, and high-speed networking capabilities.
Figure 1. Versal is suitable for HHHL, 3U VPX, VNX, OCP NIC, custom SFF, and many more acronyms. (Source: AMD)
The significance of the announcement extends beyond memory capacity. AMD has effectively created a third option between traditional external DRAM and HBM. HBM delivers exceptional bandwidth through advanced packaging technologies such as CoWoS and silicon interposers. Those approaches work well in data centers. Embedded customers often require operating temperatures down to -40°C, product support that spans more than a decade, and predictable component availability. AMD notes that HBM does not align well with those requirements because suppliers refresh products according to data center market cycles.
Memory on Package takes a different approach. AMD places standard JEDEC-compatible LPDDR5X devices on the package substrate alongside the Versal compute die. The short interconnect distances eliminate external memory routing, simplify board design, reduce validation effort, and improve signal integrity. AMD estimates more than 60% board-area savings compared with an equivalent discrete-memory implementation. The company also claims that designers can eliminate months of memory-interface design, simulation, qualification, and board-level validation work.
The target applications reveal where AMD sees demand emerging. Physical AI systems require local processing of sensor data with minimal latency. Networking platforms need larger packet buffers and faster data movement. Radar and electronic-warfare systems process large datasets in real time. Professional video systems require substantial image buffering and AI-assisted enhancement. Test-and-measurement equipment captures and analyzes increasingly large data streams. Each workload places pressure on memory bandwidth and memory capacity while operating within constrained physical footprints.
AMD also positions the device as a bridge between embedded computing and modern AI infrastructure. The inclusion of PCIe 6.0 and CXL 3.1 allows direct connection to memory expansion and pooling resources. System architects can scale memory beyond the package while maintaining access to high-bandwidth local LPDDR5X memory. Pairing the platform with AMD Epyc processors creates additional opportunities for data-intensive workloads that span networking, AI inference, security processing, and communications infrastructure.
Security remains part of the design philosophy. The device supports PCIe Integrity and Data Encryption, integrated DDR memory encryption, and dedicated 400G cryptographic engines. Those capabilities support secure communications and protected data movement without consuming programmable logic resources that customers would otherwise allocate to application development.
AMD plans to begin sampling Versal Premium Gen 2 MoP devices at the end of 2026, with production shipments expected during the second half of 2027. Existing Versal customers can adopt the new platform through established Vivado and Vitis development environments, compatible IP, and reference designs. AMD, therefore, extends the Versal platform without requiring customers to learn a new architecture or redesign existing workflows.
Memory has become a first-order design parameter. AMD’s announcement recognizes that reality. The company has chosen to address memory constraints through packaging innovation, supply-chain pragmatism, and system-level integration. For many embedded customers, that combination may matter as much as raw compute performance.
The Versal Premium Gen 2 MoP family reflects a broader shift in semiconductor design. System architects increasingly optimize complete platforms rather than individual components. Compute, memory, interconnects, power, lifecycle support, and packaging now determine system capability. AMD’s Memory on Package strategy recognizes that memory architecture has become a defining element of competitive differentiation, particularly in edge AI and embedded deployments.
What do we think?
AMD has identified a practical gap between conventional DRAM implementations and HBM-based designs. Many embedded customers need more memory bandwidth and capacity, yet they also require long lifecycles, industrial temperature ranges, predictable sourcing, and compact form factors. Memory on Package addresses those requirements with familiar LPDDR5X technology and advanced integration. The approach will appeal to designers that value deployment longevity and faster time to market as much as peak bandwidth.
The announcement signals more than a new FPGA or adaptive SoC configuration. It highlights a growing recognition that memory architecture now drives system design decisions across AI, networking, and edge computing. The industry has focused on accelerators, GPUs, NPUs, and processors for several years. Memory now moves into the foreground. If memory integration becomes a primary differentiator across embedded and AI platforms, this development may represent an inflection point in how the industry defines “system.”
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