NASA’s HPSC processor gives spacecraft a local AI computer for navigation, science, networking, and fault recovery. Microchip now productizes the design as PIC64-HPSC, a radiation-hardened RISC-V SoC with vector pipelines, deterministic Ethernet, and spaceflight-grade resilience. The architecture matters to ISVs, silicon teams, and mission architects because it supports familiar AI tools while reducing dependence on Earth-based command loops. It also shows how edge inference moves into constrained systems where latency, power, and radiation shape every design trade-off for spacecraft autonomy directly.
NASA’s High Performance Spaceflight Computing (HPSC) program gives spacecraft a new compute foundation for missions that cannot wait for Earth-based commands. Microchip Technology now productizes that architecture as PIC64-HPSC, a radiation-hardened RISC-V SoC that combines AI inference, vector processing, deterministic networking, security, and fault management in one device. NASA started the HPSC project in 2021 under the Space Technology Mission Directorate’s Game Changing Development program, and JPL selected Microchip in August 2022 through a competitive contract process.
The contract structure matters because NASA did not treat HPSC as a one-off spacecraft processor. JPL awarded Microchip a $50 million firm-fixed-price contract, and Microchip contributed its own R&D funding as part of a commercial partnership model. That structure pushes PIC64-HPSC beyond a NASA-only development path. Microchip can sell the architecture into commercial space, defense, aviation, and high-reliability edge markets, while NASA gains a processor family that can support missions over multiple decades.
Spacecraft need this class of processor because legacy rad-hard computing no longer matches the data that modern sensors generate. The RAD750 and similar processors can handle command, control, and telemetry, but they cannot efficiently run AI inference, sensor fusion, autonomous navigation, or high-rate science triage. Communication latency compounds the problem. Mars operations already face long round-trip times, and outer solar system missions face delays that make ground-loop decision cycles impractical for time-sensitive events.
HPSC moves decision-making closer to the instrument. A lander can classify terrain during descent. A rover can rank science targets before it spends energy driving. An orbiter can filter sensor data before it fills the constrained downlink capacity. A spacecraft can manage local hazards without waiting for ground operators. NASA describes this direction as AI at the edge, but the design also supports conventional HPC workloads, deterministic control, and distributed spacecraft networking.
The processor uses a cache-coherent 64-bit RISC-V architecture. It integrates 10 RISC-V cores, including eight application cores and two system controller cores. The application cores use two SiFive X288 quad-core complexes. Each complex contains four SiFive X280 cores with 512-bit RISC-V vector pipelines. Those vector units support variable-length vector execution and give the chip its main AI and scientific-computing engine.
Figure 1. PIC64-HPSC block diagram. (Source: Microchip)
NASA and its partners chose RISC-V vectors instead of a discrete NPU because spacecraft impose unusual constraints. A separate accelerator can improve peak performance, but it also adds software, verification, power, and fault-management complexity. HPSC uses one ISA, one compiler path, and one vector programming model for scalar, DSP-like, AI, and scientific workloads. That choice gives ISVs and flight software teams a simpler target than a CPU-plus-NPU-plus-FPGA architecture.
The chip delivers roughly 2 TOPS of INT8 AI performance and about 1 TFLOPS of BF16 throughput. It also reaches about 26,000 DMIPS and 46,000 CoreMark at up to 1.0 GHz. Those numbers do not compete with terrestrial AI accelerators, and they do not need to. HPSC targets workloads where power, radiation tolerance, determinism, and mission assurance matter more than rack-scale throughput. The useful comparison comes against earlier rad-hard processors, where NASA reports more than a 100× performance-per-watt gain over legacy spaceflight compute.
Table 1. Specification of High Performance Spaceflight Computing processor. (Source: NASA)
Memory bandwidth drives much of the architecture. HPSC includes dual DDR4 memory controllers with 51.2 GB/s of aggregate bandwidth, plus DMA engines that move sensor data while compute pipelines continue running. The vector cores can process image, radar, lidar, spectroscopy, and telemetry streams without forcing every byte through a ground-controlled workflow. That capability gives mission designers more freedom to build instruments that generate more data than a spacecraft can downlink.
Figure 2. High Performance Spaceflight Computing processor. (Source: NASA)
The networking block changes spacecraft architecture as much as the vector cores do. HPSC integrates a 240 Gb/s, 16-port Time-Sensitive Networking Ethernet switch with RDMA support. That switch can move data between instruments, memory, and processors without tying up the application cores. It also lets engineers design Ethernet-connected spacecraft buses and cluster multiple HPSC devices into larger rad-hard compute systems. In a low-power cruise phase, software can shut down application cores and let the chip operate mainly as a deterministic switch.
Fault tolerance shapes every part of the device. GlobalFoundries’ 12LP+ FinFET process gives the design a modern manufacturing base with radiation-resilience advantages. NASA and Microchip then add radiation-hardened-by-design logic, hardened flip-flops, ECC and EDAC on memory paths, memory scrubbing, modular redundancy, and fault containment. The architecture addresses total ionizing dose effects as well as single-event upsets, transients, latch-up, and functional interrupts.
Figure 3. Fault tolerance. (Source: Microchip Technology)
The two system controller cores anchor the fault-management model. They monitor subsystems, manage recovery, control power states, supervise mission-mode transitions, and handle safe-state procedures. Application cores can run in Dual-Core Lockstep mode. In that mode, one core executes as the main core and another executes as the shadow core. The SoC compares outputs cycle by cycle. If a mismatch appears, the system stops the operation before corrupted data reaches memory and alerts the system controller.
HPSC also supports mixed-criticality workloads. RISC-V WorldGuard and virtualization support let teams partition cores, memory, and I/O into isolated domains. One partition can run VxWorks or RTEMS for flight-critical control. Another can run Linux with AI frameworks for science analysis. A hypervisor can enforce separation between the two. That model gives spacecraft developers a way to place autonomy and safety control on the same SoC without letting experimental AI code interfere with deterministic flight software.
Power management supports mission-phase elasticity. The SoC includes more than 70 software-controlled power islands, clock gating, dynamic clock control, and sleep modes. A cruise phase can minimize energy use. Entry, descent, and landing can activate more vector compute. A science pass can prioritize instrument ingest and inference. A fault-recovery scenario can leave only the system controller and selected interfaces active. This granularity matters for spacecraft that operate under solar, battery, thermal, and radiation constraints.
The software stack may determine adoption speed. NASA and Microchip target a desktop-to-spaceflight workflow. Developers can build and validate AI models with TensorFlow, XNNPACK, OpenXLA, LLVM, OpenCL, and standard RISC-V tools before they port code into a mission environment. OpenCL support also lets software target external PCIe-attached GPUs, accelerators, or FPGAs where mission designers need more specialized hardware. That approach reduces the gap between terrestrial AI development and flight-ready deployment.
For ISVs, HPSC opens a new class of addressable platforms. Space software has historically required specialized ports, custom DSP flows, and conservative processor assumptions. HPSC gives ISVs a modern vector target, familiar AI libraries, Linux support, real-time OS support, and deterministic I/O. Aerospace customers will still demand verification, qualification, and long life cycle support, but the programming model looks much closer to terrestrial embedded AI than previous rad-hard platforms allowed.
For silicon teams, HPSC validates a vector-first approach to constrained AI. The design does not chase data-center-style tensor arrays. It uses wide RISC-V vectors, coherent multicore processing, DMA, Ethernet, and power islands to balance throughput, software simplicity, and resilience. That pattern has relevance beyond space. Defense, industrial robotics, autonomous vehicles, and remote infrastructure all face versions of the same problem: local inference under energy, safety, and reliability constraints.
HPSC does not remove the need for careful mission design. Teams still need radiation analysis, thermal planning, deterministic software, redundancy strategies, and formal verification. AI models also need validation under mission-specific sensor conditions. The chip gives developers more local compute, but it does not make autonomy free. It shifts the engineering challenge from “Can the processor run this workload?” to “Can the mission team prove this workload behaves safely?”
The broader direction looks clear. NASA, Microchip, and SiFive have aligned space silicon with open standards, modern compilers, vector AI, deterministic Ethernet, and scalable software development. That combination gives future missions a platform for local intelligence rather than a faster version of a telemetry controller. As spacecraft carry more advanced sensors and operate farther from Earth, this architecture provides mission architects with a credible path to autonomy at the point of observation.
Summary
HPSC moves space computing toward local intelligence, shared networking, and software portability. NASA and Microchip combine RISC-V vectors, AI frameworks, deterministic Ethernet, fault tolerance, security, and power elasticity in a processor that can serve rovers, landers, orbiters, satellites, and exploration platforms. The design will succeed only if silicon qualification, toolchains, and mission software mature together, but it gives aerospace teams a concrete architecture for autonomous operations beyond Earth-controlled compute loops.
What do we think?
NASA and Microchip created more than a faster rad-hard processor. HPSC gives mission teams a software-friendly AI platform that links RISC-V vectors, Ethernet fabrics, DCLS, and mixed-criticality isolation. Silicon teams should watch the vector-first AI choice. ISVs should test toolchains early. Program leaders should track delivery maturity before committing flight software schedules to the platform across missions and payloads classes.
HPSC marks an inflection point for AI because it moves inference, sensor triage, and autonomy into radiation-hardened space computers rather than ground loops. This inflection point does not make the spacecraft independent overnight, but it changes system design assumptions. Mission teams can plan instruments, networking, and software around local decisions. If adoption follows testing, deep-space platforms will treat AI compute as core infrastructure instead of an optional payload feature. That shift will influence aerospace, defense, robotics, and industrial edge systems, too.
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