Apple just shipped its first 2 nm chip and paired it with the most powerful silicon the company has ever built. M6 lands in a refreshed Mac mini, combining all three of Apple’s core types on one die for the first time. M5 Ultra fuses four dies into a single quad-die processor inside the new Mac Studio, built specifically for people running large AI models entirely on their own desktop. We walk through the real specs behind both chips, what changed, and what stayed the same.
Apple’s new M6 processor moved to TSMC’s 2 nm process, the first Apple silicon built on that node, and it’s the first Apple chip to combine super cores, performance cores, and efficiency cores together on a single die. The 12-core CPU complex splits into two super cores, four performance cores, and six efficiency cores, two more cores total than M5.
Super cores themselves debuted earlier, on M5 Pro and M5 Max in March; M6 is the first chip to run all three tiers at once. Apple states the world’s fastest single-threaded performance from this configuration is up to 1.2× the multithreaded throughput of M5, and up to 2.4× faster performance than M1, the baseline Apple keeps returning to for long-arc comparisons across the M series. The super cores absorb single-threaded work directly, the performance cores join them for demanding multithreaded jobs at lower power draw, and the efficiency cores handle background tasks without pulling from the same power budget.
Apple names four workloads this configuration targets directly: editing images, compiling code, indexing new files, and running agentic AI workloads, all tasks that stress a mix of single-threaded responsiveness and sustained multithreaded throughput at once.
Figure 1. Generalized block diagram of Apple’s new M6 multi-multi-processor with NPU.
The GPU grows to 12 cores, also two more than M5, with a Neural Accelerator built into every core. That configuration delivers close to 30% more peak GPU compute for AI than M5, over 8× more than M1, and Apple points to faster prompt processing for on-device LLMs as the direct result. Graphics gains come from an updated shader core architecture, refreshed dynamic caching, hardware-accelerated ray tracing, and 50% higher geometry rates. A dual 16-core Neural Engine rounds out the AI compute picture, delivering up to 2× the peak compute of the previous generation, with system frameworks able to dispatch work to both engines at the same time.
NPUs everywhere
Functionally, the Neural Accelerator built into every core is the same core idea as an NPU: a dedicated unit built specifically for fast matrix multiply-accumulate operations, the fundamental math neural networks run on. Architecturally, it’s the same pattern as Nvidia’s Tensor Cores—a small matrix-math block embedded inside each individual compute unit (each Streaming Multiprocessor for Nvidia, each GPU core for Apple), rather than existing as its own separate chip. That’s exactly the “embedded, one-per-core” pattern we classified plenty of chips under in the NPU list.
And there’s also a genuinely separate, stand-alone NPU in the same chip
Apple’s Neural Engine (dual 16-core on M6, 32-core on M5 Ultra) is architecturally distinct silicon, not just a bigger version of the per-core Neural Accelerators. Academic literature confirms the three-way split directly: Apple Silicon integrates CPU, GPU, and Apple Neural Engine (ANE) as three separate blocks sharing one unified memory pool, not two blocks with a bigger one. The Neural Engine traces back to the A11 Bionic in 2017 and has always been Apple’s dedicated NPU lineage, completely separate from graphics compute.
The real, practical difference: how you actually reach each one.
This is the part worth knowing if you’re classifying these for the tracker: The two aren’t just architecturally separate; they’re programmed completely differently.
Unified memory bandwidth reaches up to 170 GB/s, a 10% increase over M5 and 2.5× over M1. Capacity caps at 32 GB, a real ceiling for anyone running larger local models. Storage runs at up to 15 GB/s, twice the previous rate. Every gain lands inside the same power envelope Apple has held across the M series, keeping performance per watt as the through-line across CPU, GPU, and Neural Engine.
The Neural Accelerator placement is worth pausing on for silicon teams specifically: Putting one inside every GPU core, instead of isolating AI compute into a single separate block, mirrors the “tensor core per streaming” multiprocessor pattern other GPU architectures use, and it means graphics and AI workloads share the same execution resources instead of contending for a fixed-size dedicated unit. That architectural choice scales cleanly from M6’s 12 GPU cores to M5 Ultra’s 80, the same design principle applied at two very different sizes.
Figure 2. Generalized block diagram of Apple M5 Ultra processor—M5 Ultra—quad-die Mac Studio, 36-core CPU.
The 3 nm M5 Ultra takes a genuinely different architectural path. UltraFusion connects two dual-die M5 Max chips into a single quad-die package, Apple’s first quad-die design in the M series. Inter-die bandwidth crosses 4.4 TB/s, connection density grows more than 6× over the previous UltraFusion generation, and the four dies operate as one processor, not four coordinated ones. That distinction matters directly for software: The operating system and applications see a single chip, not a cluster.
The CPU scales to 36 cores, 12 super cores plus 24 performance cores, delivering up to 1.25× higher single-threaded performance and 1.3× higher multithreaded performance than M3 Ultra. The GPU scales to 80 cores, each carrying a Neural Accelerator, for up to 4.5× the peak AI compute of M3 Ultra and more than 6× M1 Ultra. The same shader core architecture, second-generation dynamic caching, hardware-accelerated mesh shading, and third-generation ray tracing that appear across the line combine here for up to 40% faster graphics than M3 Ultra. A 32-core Neural Engine and a more capable Media Engine, four ProRes encode/decode engines plus hardware AV1 decode, round out the chip.
Memory tops out at 512 GB, running at 1.2 TB/s of unified bandwidth, 50% higher than M3 Ultra. That combination lets an entire large language model with hundreds of billions of parameters sit fully in local memory, raising tokens-per-second throughput and removing any need to page data in from storage mid-inference. Apple positions the chip specifically for complex 3D rendering, visual effects work, scientific analysis, and running compute-intensive frontier AI models directly on device—workloads that share one trait: They need enough memory capacity to hold an entire working dataset at once, not just enough compute to process it quickly.
That memory capacity arrives against a genuinely difficult supply backdrop for the whole industry, not just Apple. DRAM pricing rose roughly 90% quarter over quarter in Q1 2026 and another 50%-plus in Q2, and IDC describes the underlying cause as a structural reallocation of wafer capacity: Every wafer fabricated as HBM for AI accelerators is one wafer that doesn’t become standard RAM for a laptop or desktop. Apple pulled its largest memory configurations from sale entirely earlier in 2026 before restoring them here, and the 512 GB M5 Ultra configuration specifically won’t ship until late October, a month after the rest of the lineup, pointing to real constraints on the memory supply behind these specs, not just a staggered rollout schedule.
Table 1. Comparison of M6 to M5 Ultra. (Source: Apple)
One detail cuts against the usual pattern: The cheaper machine carries the newer process node, and the flagship chip stays on M5’s 3 nm process. Ultra parts assemble from Max dies and always trail a generation behind, so this isn’t new for Apple. It means the M5 Ultra name undersells how large a jump it represents in AI workloads, even on an older node. Apple’s roadmap skips an M6 Pro and M6 Max entirely, moving straight to M7 in mid-2027.
Mac Studio now supports clustering over Thunderbolt 5 with RDMA, pooling memory across multiple machines instead of treating each as an isolated system. Four clustered Studios reach up to 3× the inference throughput of a single machine, according to Apple. MacOS 26.2 laid the groundwork for this last December, adding low-latency communication between Thunderbolt 5 hosts specifically for distributed inference through MLX, and developers had already started daisy-chaining Mac minis and Studios to run models too large for any single consumer machine to hold. A new Core AI framework joins MLX as the software layer developers build on.
Apple’s developer stack, Core AI, Core ML, Metal, and Xcode, taps directly into both chips’ hardware. Developers get access to the dual 16-core Neural Engine on M6 and the Neural Accelerators across M5 Ultra’s 80-core GPU, alongside its 512 GB memory pool, with the frameworks automatically handling optimization across CPU, GPU, and Neural Engine. Apple Foundation Models and App Intents give developers a path into Apple Intelligence directly, or a path to run proprietary models entirely on device instead.
Both chips ship September 22, with the 512 GB M5 Ultra configuration arriving in late October. Apple’s John Ternus takes over as CEO September 1, making this launch the final product shipped under Tim Cook, and the specs above will set the baseline every M7 comparison will measure against.
What do we think?
M6’s real story is architectural, not raw speed: Running all three core tiers together on one die, at 2 nm, sets the template future M-series chips follow. M5 Ultra matters more for what it enables than what it benchmarks against, an older process node still pushing 512 GB of pooled memory and desktop-cluster inference, positioning Apple hardware as an alternative to cloud GPU rental.
Inflection point. The real signal isn’t the 2 nm process or the quad-die package, it’s Thunderbolt 5 RDMA clustering turning ordinary desktops into a distributed inference cluster. If four Mac Studios genuinely deliver 3× the throughput of one, Apple has built a credible on-premise alternative to renting cloud GPU capacity, not just a faster workstation. That’s the inflection point worth watching: AI infrastructure decisions shifting from a cloud-only default toward a real hardware-purchase decision, decided by memory capacity and interconnect bandwidth, not raw FLOPS alone.
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