Chiplets need a home—UCIe has one for them

Intel creates a universal interconnect consortium

Jon Peddie

Universal Chiplet Interconnect Express (UCIe) is an open specification that defines the interconnect between chiplets within a package, enabling an open chiplet ecosystem and ubiquitous interconnect at the package level. Forming an open industry standard organization around UCIe are Advanced Semiconductor Engineering (ASE), AMD, Arm, Google Cloud, Intel, Meta, Microsoft, Qualcomm, Samsung, and TSMC.

The feasibility of implementing complex systems on monolithic dies is reaching its physical and economic limits. Gordon Moore predicted this “day of reckoning” in his seminal 1965 white paper, “Cramming More Components onto Integrated Circuits,” writing that as chip density and complexity progressed, eventually “it may prove to be more economical to build large systems out of smaller functions, which are separately packaged and interconnected.”

Chiplets give designers greater flexibility, open new frontiers for reuse, and enable innovation on price, performance, and power consumption across the compute continuum. “Moore foresaw this day. Now we believe chiplets are the key to extending Moore’s law through the next decade and beyond. Our consortium colleagues agree,” said Kurt Lender, IO Technology Solution Team Strategist at Intel. “And we’ll get to the next set of computing breakthroughs faster if we begin by settling on a well-defined specification. With Intel’s experience building these systems, we were able to donate a mature spec to the consortium that gave us a starting place. After feedback from the other founding members, our working group quickly ratified a 1.0 specification that works for everyone.”

Membership in the UCIe Consortium is open to all companies in the industry that want to help enhance the UCIe specification. The consortium expects rapid uptake among its colleagues up and down the silicon value chain—and they encourage industry-wide participation in future UCIe specifications.

Moving to a chiplet architecture will bring other benefits to the industry, too. Customers will be able to leverage different manufacturers more easily for any component of their solutions, motivating manufacturers to deliver new levels of quality, price, and customer service. Competition will take place on a level playing field, where products and services are the differentiators, not artificially constrained ecosystems or technological incumbency.

What do we think?

UCIe is a critical component of Intel’s IDM 2.0 strategy. This specification builds on Intel’s open Advanced Interface Bus (AIB) and should enable flexibility, a cost-effective (and fast) way to provide solutions, and most importantly, the ability to use the right chiplet for the job—regardless of who makes it.

Going forward, we expect to see more SoP designs that feature Intel silicon alongside chiplets from other foundries. This is a new era of semiconductor architecture that puts designers in control and presumably continues Moore’s vision of doubling computing power into the future.

More information and testimonials here.  Intel, building a chiplet ecosystem