Codasip launched a new low-power core, Codasip L110, and updated Codasip Studio with Bounded Customization for faster RISC-V custom core deployment. Codasip says L110 offers better performance per watt and a smaller code size. The offerings together should enable quick deployment of custom, efficient cores.
What do we think? Despite some initial skepticism, Codasip’s “tools first” business model has proven to have legs, and, arguably, the company is more attractive today than other RISC-V IP rivals like SiFive or Andes. That’s good timing, as the RISC-V IP market is due some M&A activity, we think. The ability to customize within boundaries should both de-risk and speed up core development. Hopefully, the next breakthrough will be to do the same with more powerful cores.
Codasip aims at lower-risk processor design and verification for RISC-V
Codasip has introduced a new low-power embedded processor core and the next generation of its processor design automation toolset, Codasip Studio.
The Codasip L110 core targets power-sensitive applications and enables customers to add unique customizations. A new level of customization in Codasip Studio Fusion, Bounded Customization, is designed to achieve a fast time to market for fully verified RISC-V cores by protecting the functionality of the baseline core. A new verification framework then simplifies the verification of the custom instructions.
The company claims Codasip L110 delivers up to 50% improvements in performance per watt and 20% smaller code size compared to similar cores in the market.
Codasip CEO Ron Black told us: “L110 is a solid choice for anyone needing a small, power-efficient embedded processor. Even though the benchmarks knock other cores out of the park, it’s not even the best part of this launch. We’re introducing Bounded Customization, enabling customers to get to market fast with a fully verified custom core. No one else can offer this combination of performance and flexibility.”
Bounded Customization means that using Codasip Studio Fusion, custom instructions can be added without risk, according to Codasip, by following a set of rules allowing for many common customizations. You can then generate a custom register transfer level (RTL) and software development toolkit with a compiler that understands your custom instructions.
The functionality of the baseline core is unmodified, and the provided verification framework makes the verification of the custom instructions more straightforward. This could mean a substantially shorter time to market for a fully verified custom core.
For customers in need of a starting point with higher performance, Codasip offers other options such as the A730 64-bit RISC-V application core.
All of this is offered in what Codasip describes as “a flexible business model that will not cost you an arm and a leg.”