SiFive opens its Kernel Library to the RISC-V community
SiFive releases optimized RISC-V AI kernels as open source.
Condor flies no more
How an Austin start-up set out to push RISC-V into the data center but fell short.
Andes teaches its RISC-V edge platform to speak transformer
Andes upgrades the AnDLA I370 for ViT, VLM, and small language models at the edge.
Q2’26 RISC-V Market Update from Jon Peddie Research
RISC-V enters the AI silicon fight: Open ISA meets memory, sovereignty, consolidation.
Semidynamics wants to make memory the metric that matters
Semidynamics brings a memory-first inference stack to ISC.
K210 puts RISC-V AI on the edge in 2018
Kendryte chip proved edge AI inference could run on a coin cell—then Canaan pulled the plug.
Vortex expands open RISC-V graphics
Version 3.0 adds graphics and AI.
Asygn’s Colibry NPU tries to make edge AI live on scraps of power
Asygn wants Colibry to bring vision AI to the smallest devices.
GlobalFoundries adds ARC to MIPS and tightens its grip on the RISC-V stack
GF completes ARC acquisition and folds it into MIPS.
SiFive moves RISC-V closer to the mainstream
SiFive’s P570 Gen 3 targets the useful middle of RISC-V compute
Tenstorrent goes general-purpose in an age of AI specialization
Company says one system can do the whole inference job.
RISC-V becomes AI hardware’s open foundation
Three integration tracks move RISC-V beyond CPU control.