Vortex expands open RISC-V graphics
Version 3.0 adds graphics and AI.
Asygn’s Colibry NPU tries to make edge AI live on scraps of power
Asygn wants Colibry to bring vision AI to the smallest devices.
GlobalFoundries adds ARC to MIPS and tightens its grip on the RISC-V stack
GF completes ARC acquisition and folds it into MIPS.
SiFive moves RISC-V closer to the mainstream
SiFive’s P570 Gen 3 targets the useful middle of RISC-V compute
Tenstorrent goes general-purpose in an age of AI specialization
Company says one system can do the whole inference job.
RISC-V becomes AI hardware’s open foundation
Three integration tracks move RISC-V beyond CPU control.
Banana Pi gives RISC-V an edge AI board for large local LLMs
Launches a 60 TOPS RISC-V AI developer kit.
Q1’26 RISC-V Market Update from Jon Peddie Research
Platform economics drive consolidation as buyers favor integrated deliverables over per-core IP.
SiFive raises again as CPUs return to the center of the AI data center story
$400 million gives SiFive space ahead of a probable IPO.
Codasip bets the company on secure compute
Codasip pivots to CHERI-led cyber resilience after portfolio realignment.
Allen Wu’s open hardware playbook
Interview with Allen Wu, founder and chairman, CoreLab Technology.
Alibaba’s RISC-V CPU runs AI natively
Using vector engine rather than NPU.