Edge AI moves closer to sensors
Low-power compute brings inference closer to motion.
SiFive moves RISC-V closer to the mainstream
SiFive’s P570 Gen 3 targets the useful middle of RISC-V compute
If you want to do AI, you need an NPU, right?
Wrong. Just a processor that can do matrix math and doesn’t have to be dedicated.
Banana Pi gives RISC-V an edge AI board for large local LLMs
Launches a 60 TOPS RISC-V AI developer kit.
Ubitium bets one RISC-V chip can clean up embedded computing’s processor sprawl
Ubitium tapes-out first silicon for its universal embedded processor.
Interview with Steve Roddy, chief marketing officer, Quadric, Inc.
Quadric’s bet on software-first NPUs starts to pay off.
Interview with MIPS: Drew Barbier and James Prior
MIPS’ unlikely rise to deliver RISC-V at ‘foundry scale.’
Interview with Innatera CEO Sumeet Kumar
Spiking neuromorphic for the edge in real devices.
Axelera steps into the spotlight at CES with real-world edge AI
Metis AIPU shipping for a wide range of edge applications.
Ceva’s CES: Three wins that map the edge-AI stack from wake word to zonal control
Ceva stacks automotive sensing + real-time control, while tightening its ultra-low-power voice story.
Pocket accelerator vs. desk supercomputers: Tenstorrent picks a different fight
The new local AI arms race: A tale of three boxes.
Ambiq puts edge AI on a power diet
Atomiq, a SPOT-optimized NPU SoC for low-power AI at the edge.