Asygn’s Colibry NPU tries to make edge AI live on scraps of power
Asygn wants Colibry to bring vision AI to the smallest devices.
GlobalFoundries adds ARC to MIPS and tightens its grip on the RISC-V stack
GF completes ARC acquisition and folds it into MIPS.
Edge AI moves closer to sensors
Low-power compute brings inference closer to motion.
SiFive moves RISC-V closer to the mainstream
SiFive’s P570 Gen 3 targets the useful middle of RISC-V compute
If you want to do AI, you need an NPU, right?
Wrong. Just a processor that can do matrix math and doesn’t have to be dedicated.
Banana Pi gives RISC-V an edge AI board for large local LLMs
Launches a 60 TOPS RISC-V AI developer kit.
Ubitium bets one RISC-V chip can clean up embedded computing’s processor sprawl
Ubitium tapes-out first silicon for its universal embedded processor.
Interview with Steve Roddy, chief marketing officer, Quadric, Inc.
Quadric’s bet on software-first NPUs starts to pay off.
Interview with MIPS: Drew Barbier and James Prior
MIPS’ unlikely rise to deliver RISC-V at ‘foundry scale.’
Interview with Innatera CEO Sumeet Kumar
Spiking neuromorphic for the edge in real devices.
Axelera steps into the spotlight at CES with real-world edge AI
Metis AIPU shipping for a wide range of edge applications.
Ceva’s CES: Three wins that map the edge-AI stack from wake word to zonal control
Ceva stacks automotive sensing + real-time control, while tightening its ultra-low-power voice story.