Jon Peddie Research (JPR) has prepared a new white paper, “Rethinking Edge AI Costs: RRAM vs. Digital ASICs,” examining the system-level economics of analog in-memory computing (A-IMC) using resistive random-access memory (RRAM) and conventional digital application-specific integrated circuits (ASICs). The paper evaluates how model storage, data movement, manufacturing, testing, and software integration influence the cost of deploying AI inference at the edge.
RRAM A-IMC arrays store neural network weights as resistance states and perform selected matrix operations in or near the memory structure. This approach can reduce repeated transfers of model weights between memory and compute units. Digital ASICs use established CMOS processing and memory hierarchies, including on-chip SRAM and external DRAM where model capacity requires it.
The report finds that RRAM integration may reduce external weight-memory requirements, printed circuit board complexity, and power consumption for suitable workloads. Those potential savings must account for analog-to-digital conversion, calibration, device variability, additional fabrication steps, and testing. Digital ASICs offer mature manufacturing processes, software ecosystems, and predictable characterization methods. Both architectures can avoid external DRAM for sufficiently small models.
Figure 1. Analog RRAM architecture integrates weight storage and selected computation.
The white paper examines the cost of the complete edge AI system, including the processor, memory, board area, packaging, power delivery, thermal management, manufacturing yield, and long-term support. It also discusses production sourcing and the measurements that developers should request before comparing accelerator designs.
“Edge AI economics depend on the entire system,” said Dr. Jon Peddie, president of Jon Peddie Research. “RRAM offers opportunities to reduce memory, power, and packaging costs, but manufacturing yields and software determine commercial success.”
For ISVs and silicon development teams, the report highlights compiler support, operator coverage, precision, calibration, and model-mapping requirements. For CIOs and IT decision-makers, it emphasizes workload-specific performance, deployment cost, maintenance, and supply-chain risk.
The report recommends evaluating competing solutions using the same inference workload, accuracy target, operating conditions, and system boundaries. It cautions against treating peak TOPS/W figures or processor unit prices as complete measures of deployment economics.
“Rethinking Edge AI Costs: RRAM vs. Digital ASICs” is a Jon Peddie Research white paper. For availability and additional information, call (415) 435-9368 or visit the Jon Peddie Research website.