Weebit Nano has launched its Matrix In-Memory Compute Research Program, giving researchers access to real ReRAM silicon to explore new AI computing architectures. Early results suggest substantial improvements in power efficiency and latency, particularly for edge AI inference. JPR examines the technology’s potential, the challenges of commercialization, and why in-memory computing could become an important alternative to conventional digital architectures.
(Source: Weebit Nano/JPR AI)
Weebit Nano has launched the Weebit Matrix In-Memory Compute (IMC) Research Program, providing researchers with access to real ReRAM silicon to explore new AI computing architectures.
The program provides development kits based on Weebit’s resistive random-access memory (ReRAM) technology, allowing academic and industrial researchers to investigate analog computing, neural network inference, and neuromorphic architectures.
The announcement represents an expansion of Weebit’s ambitions beyond its established embedded non-volatile memory business. Although the company is already commercializing ReRAM IP for conventional memory applications, in-memory computing offers an opportunity to use the same underlying technology to perform computation itself.
AI processing increasingly involves moving large volumes of data between memory and processing units. That movement consumes power, introduces latency, and can constrain performance. In-memory computing addresses the problem by performing calculations directly where the data is stored.
ReRAM is particularly interesting because its electrical characteristics allow it to perform analog calculations. Neural network weights can be represented by the conductance of individual memory cells. Applying an input voltage produces a current proportional to the stored weight, using Ohm’s law. The currents can then be accumulated across a crossbar array using Kirchhoff’s law, effectively performing multiply-accumulate (MAC) operations without conventional digital multipliers or repeated movement of weights.
These characteristics make ReRAM particularly attractive for inference workloads, where weights are read repeatedly but updated relatively infrequently.
From simulations to silicon
The Weebit Matrix platform uses a 32×32 crossbar array containing 1,024 individually selectable ReRAM cells in a one-transistor, one-resistor (1T1R) architecture.
The research chip is deliberately simple, containing the analog array without integrated digital processing or peripheral conversion circuitry. Researchers can access individual memory cells and control the electrical signals to investigate programming, multiple resistance states, device behavior, and computational accuracy.
Two packages are available. The Matrix IMC Evaluation Package provides direct analog access for electrical characterization and device-level research. The Matrix IMC Quick-Start Package adds FPGA-based control, data conversion, and example code for exploring matrix-vector operations and neural network inference.
Both packages include 10 packaged ReRAM array samples and documentation.
Speaking to us ahead of the launch, Eran Briman, who heads marketing and business development at Weebit, explained that the program was prompted by requests from universities, research institutes, and semiconductor companies wanting to move beyond simulations and experiment with actual devices.
Weebit has already been working with researchers on IMC and neuromorphic computing. The new program formalizes this collaboration, with participants sharing ReRAM-related findings to help develop programming methods, software tools, and new architectures.
Briman said: “Most of the initial interest is in edge AI, where relatively small models have to operate with very low power consumption and latency. Automotive sensors, industrial equipment, and other embedded applications are especially promising.”
Although data center applications are also being explored, they present different challenges, including larger models and the need for more advanced semiconductor process nodes.
Weebit’s broader ReRAM development has reached 22nm. However, extending IMC to the most advanced process nodes remains a longer-term opportunity.
The company says its eventual objective is to license IMC IP for integration into customers’ processors and system-on-chip designs, rather than develop competing AI processors of its own.
Early results
Weebit has also disclosed results from a US-based company developing radiation-tolerant AI hardware, which investigated ReRAM-based processing for space-related applications, including image analysis for potential NASA missions. The project implemented neural network operations using Weebit ReRAM arrays and compared an IMC architecture with GPU- and FPGA-based alternatives.
Based on measured ReRAM hardware behavior and application-level modeling, the researchers projected that an IMC implementation could consume approximately 80 times less power than the GPU approach, while reducing inference latency by almost 100 times.
The comparison estimated power consumption of 0.8 W for the IMC system against 69.6 W for an Nvidia GeForce RTX 4090 implementation, with latency falling from 47.5 ms to 0.5 ms.
These are projected system-level results rather than measurements from a completed commercial IMC accelerator, but they indicate the potential advantages of the architecture for highly constrained applications.
At electronica 2026, Weebit says it will demonstrate an edge-detection application using two ReRAM evaluation boards connected to an FPGA. The system processes images from a USB camera, with the same edge-detection algorithm running in parallel on an Nvidia RTX 5070 GPU. According to Weebit, the two approaches produce nearly identical edge-detection outputs, illustrating how analog ReRAM arrays can perform convolution and multiply-accumulate operations relevant to AI workloads..
The company also highlighted ReRAM’s inherent radiation tolerance, which should make the technology potentially attractive for aerospace, defense, and other environments where conventional electronics face additional reliability challenges.
What do we think?
We believe that innovative computing architectures will be essential to the continued expansion of AI, particularly at the edge. Simply increasing processing performance and memory bandwidth is unlikely to provide the efficiency improvements required across the enormous range of emerging AI applications.
In-memory computing is one of the most promising approaches because it addresses the problem at an architectural level. Rather than moving data faster between memory and processing units, it reduces the need to move that data at all.
ReRAM-based analog computing takes this further by exploiting the physical characteristics of the memory technology to perform mathematical operations. For appropriate workloads, this could offer substantial advantages in power consumption, latency, and potentially total system cost.
As we discussed in our recent white paper, Rethinking Edge AI Costs: RRAM vs. Digital ASICs, the economics of edge AI depend on considerably more than the performance of the computing array. Digital ASICs are highly optimized, benefit from established manufacturing processes and software ecosystems, and can often accommodate smaller AI models entirely within on-chip memory. External DRAM is not an inevitable requirement.
Analog IMC must also account for peripheral circuitry, data conversion, calibration, device variability, precision, and the software required to map neural networks efficiently onto the hardware. Its potential advantages must survive integration into a complete system. This is why the distinction between measured device performance and projected system-level results matters. Large improvements compared with a general-purpose GPU are encouraging, but the more meaningful commercial comparison will be against optimized digital edge AI implementations running equivalent workloads at comparable accuracy.
Weebit, nevertheless, has an interesting advantage over many companies researching alternative computing architectures. Its underlying ReRAM technology has already progressed through foundry integration, qualification, and commercial licensing. It is based on materials and processes compatible with conventional semiconductor manufacturing. The initial 32×32 arrays are a research tool, not a complete AI inference processor. Nevertheless, we see this as an important direction for edge AI.
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