Andes Technology has upgraded its AndesAIRE AnDLA I370 accelerator and neural network software stack to support Vision Transformers, vision-language models, and small language models at the edge. The announcement is an evolution of the I370 technology introduced in June 2025, which was primarily aimed at conventional vision, audio, and recurrent neural network inference. The new hardware and software features reflect the changing requirements of edge AI, where memory movement, model optimization, and programmability increasingly matter as much as raw arithmetic throughput.
(Source: Andes and JPR)
Andes Technology has released version 2.0 of its AndesAIRE AnDLA I370 deep learning accelerator IP, accompanied by version 1.2.0 of the AndesAIRE neural network SDK. The updated platform is intended to bring transformer-based models including Vision Transformers, vision-language models, and small language models, to power-, memory-, and cost-constrained edge systems.
This is not the first appearance of the I370. Andes announced the original accelerator in June 2025 as the successor to its I350, adding support for recurrent neural networks, audio and voice processing, INT16 data, configurable memory, and configurable bus widths. That first version was rated at up to 2 TOPS per GHz and supported frameworks including TensorFlow Lite, PyTorch, and ONNX through the accompanying AndesAIRE software stack. We interviewed the Andes team in November of 2025.
Figure 1. Andes AnDLA I370 block diagram. (Source: Andes)
The original I370 broadened the range of relatively established edge-inference workloads that Andes could address. Version 2.0 is aimed at the less accommodating world of transformer models, which can rapidly overwhelm an accelerator originally optimized around convolutional neural networks.
To address those workloads, the I370 v2.0 can be configured with between 32 and 2,048 multiply-accumulate units. Its AXI interface can scale to 512b, while additional outstanding DMA requests are intended to improve memory utilization when processing larger models. Andes has also added native division and square root operations, operator fusion, and what it calls a Programmable Tensor Operator Set Architecture for supporting transformer networks.
The inclusion of division and square root operations may appear less exciting than another large TOPS number, but it is relevant. Transformer execution includes normalization and other operations that do not map neatly onto simple matrix-multiplication arrays. Keeping more of those functions inside the accelerator reduces the need to hand work back to the host processor, with the associated data movement and latency.
The software changes may be more important than the additional MACs. AndesAIRE NN SDK v1.2.0 supports attention mechanisms and separates the prefill and decode phases of small language-model inference. It also manages KV-cache placement and memory scheduling, two increasingly important considerations when trying to fit language models into constrained memory systems.
The SDK now includes Linux kernel-mode drivers and a user-space runtime, as well as support for real-time operating systems. Task preemption is available in the RTOS environment, allowing higher-priority inference jobs to interrupt less urgent work.
Andes has also added Model Advisor and Hardware Advisor tools intended to help developers balance cost and performance when selecting hardware configurations. Word-level knowledge distillation can be used to compress a larger teacher model into a smaller model suitable for deployment on the accelerator. The software has been rebased around current LiteRT and LiteRT for Microcontrollers frameworks and supports the MLPerf Tiny v1.4 benchmark suite.
“Bringing transformer models and VLMs to cost-sensitive edge devices is arguably one of the toughest engineering problems in the current AI landscape,” said Charlie Su, CTO and president of Andes Technology.
Andes is positioning the updated platform for smart cameras, industrial automation, robotics, wearables, and edge gateways. These are markets where local inference can reduce network traffic and latency while allowing sensitive sensor data to remain on the device. They are also highly fragmented markets, with widely differing requirements for power, memory, real-time behavior, and model complexity.
What do we think?
Andes has not disclosed power consumption, silicon area, model sizes, measured token rates, end-to-end latency, or customer implementations for the new configuration. The range of 32 to 2,048 MACs demonstrates configurability, but without clock frequency, precision, memory configuration, and process information, it cannot tell us how a finished implementation will perform.
This development follows our thesis that AI is becoming the most important commercial use case for RISC-V, particularly at the flexible and heterogeneous edge.
RISC-V is unlikely to displace established GPU platforms in the data center simply by offering another general-purpose CPU instruction set. Its more immediate opportunity lies in systems where chip designers need to combine control processing, real-time execution, signal processing, security, and dedicated AI acceleration within tightly defined power and cost envelopes.
There is no single edge-AI workload. A smart camera, hearing device, industrial robot, vehicle controller, and wearable assistant may all use neural networks, but they have little else in common. They operate under different latency requirements, memory constraints, safety expectations, operating systems, and power budgets. A fixed accelerator paired with a fixed processor configuration will, therefore, leave performance, power, or silicon area on the table in at least some applications.
RISC-V gives SoC developers greater scope to tune the processor and surrounding system to the workload. Andes is extending that flexibility beyond the CPU by offering a configurable accelerator, programmable tensor operations, selectable MAC resources, adjustable memory interfaces, and a software stack intended to map models onto the resulting hardware.
Andes is not merely offering a CPU core that can sit beside somebody else’s NPU. It is building a licensable edge-AI subsystem in which the control processor, accelerator, runtime, model-conversion tools, and operating system support can be developed together.
That is potentially more valuable to customers than another stand-alone inference engine. It can reduce integration work and give designers more freedom to produce domain-specific silicon without having to assemble the entire hardware and software chain themselves.
Andes deserves credit for moving with the workload. However, it still has to demonstrate that the architecture can execute useful models at commercially attractive power, area, and latency. Transformer support on a feature list is not the same thing as a product shipping in a high-volume SoC.
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