Semidynamics at ISC High Performance 2026 in Hamburg, Germany, argues that the next phase of AI infrastructure competition will be decided less by peak TOPS and more by memory architecture. The Barcelona company has taped-out a 3 nm chip with TSMC and is pitching a rack-scale inference stack built around RISC-V, tensor compute, LPDDR capacity, and its Gazzillion latency-tolerance subsystem. The claim is: Inference economics are now memory economics.
Semidynamics booth at ISC HP 2026. (Source: JPR)
Semidynamics used ISC High Performance 2026 in Hamburg, Germany, to make a pointed argument: AI compute is only useful if the memory system can keep it fed. ISC positions itself around the convergence of HPC, AI, and quantum computing, making it a useful venue for the company, which is trying to move into the broader infrastructure conversation.
The Barcelona-based company is developing a full inference platform, from core to rack. That includes its Inference Engine, a 64-bit out-of-order RISC-V core with integrated vector and tensor units; a 3 nm Inference SoC; an inference board that pairs host compute with Semidynamics accelerators over a high-bandwidth fabric; and a liquid-cooled, OCP-compliant rack aimed at standard data center integration.
“You need serious compute to play in AI inference, and we built it,” said Roger Espasa, CEO of Semidynamics. “But compute you can’t feed is wasted silicon. The hard, still-unsolved problem is the memory architecture that keeps every tensor unit working, and that is what we designed from the core up. Our 3 nm silicon is the proof it works.” (Semidynamics recently completed its first 3 nm tape-out with TSMC, one of the first such tape-outs by a European semiconductor company.)
Figure 1. Semidynamics CEO Roger Espasa at ISC HP 2026. (Source: JPR)
Semidynamics’ central bet is that inference, especially large-scale LLM inference, is becoming a data-movement and memory-residency problem as much as a compute problem. The company has described its Gazzillion technology as a latency-tolerance subsystem embedded across the processor, from the core and tensor unit to the memory subsystem, with the goal of keeping the system productive during memory accesses that would stall conventional accelerators.
Semidynamics says it has an architecture that makes inexpensive, high-capacity LPDDR usable for inference. In a market where HBM supply, cost, and packaging complexity have become strategic constraints, that is attractive.
From XPU tray to liquid-cooled rack
The most useful new detail from ISC is the physical system architecture. Semidynamics is not only talking about an SoC or accelerator board; it is describing a complete rack design.
A representative Semidynamics rack includes CPU trays and XPU trays. The company’s example configuration has two XPU trays for each CPU tray. Each XPU tray contains two Semidynamics XPUs. Each CPU tray contains two multi-core CPUs, with x86 options from AMD and Arm options expected through partners including SiPearl.
In the middle of the rack are switches for scale-up connectivity, while the top of the rack carries the top-of-rack switch for scale-out networking. At the bottom is a coolant distribution unit, or CDU, for liquid cooling. Coolant is supplied through a manifold to both CPU and XPU trays.
That layout matters. It shows Semidynamics is thinking in terms of deployed infrastructure, not just silicon. Nvidia’s success in AI infrastructure has come from selling complete systems, not simply from selling accelerators. Any challenger has to engage at that same system level.
Semidynamics says each XPU will have performance comparable to Nvidia Rubin-class GPUs, while offering better power characteristics than Nvidia. Those are big claims, and they show that this is meant to compete with the next generation of high-end AI infrastructure, not with boutique RISC-V experiments.
Availability is expected around mid-2028. That gives Semidynamics time to finish silicon, boards, cooling, software, and rack validation. It also means the comparison point is not today’s H100 or even Blackwell deployment cycle, but the Rubin-era AI infrastructure market.
Semidynamics says its software model is designed to be standard. The company says developers should be able to work through LLVM and PyTorch, and that the rack should support familiar infrastructure tools such as Kubernetes and Slurm. Semidynamics’ software stack, including the Aliado Orchestrator and AKL kernel library, is intended to support tools AI teams already use, including vLLM, PyTorch and ONNX Runtime, with support for models such as Llama and DeepSeek directly from Hugging Face. The company’s pitch is that users should not feel a major difference from programming Nvidia Rubin-class racks.
Europe is trying to build sovereign AI infrastructure, and Semidynamics is positioning itself as a European company with European-designed compute at a time when governments are asking how much of the AI stack they can control.
The company recently announced a strategic cooperation with SiPearl to develop a European rack-scale AI compute platform for large-scale cloud inference. The concept combines SiPearl’s Arm-based CPU for host compute and orchestration with Semidynamics’ RISC-V-based inference accelerator. The availability of AMD x86 CPU options alongside SiPearl Arm CPUs also suggests Semidynamics wants to avoid becoming too tightly coupled to a single host architecture.
This is where the story becomes interesting. Europe has plenty of AI infrastructure ambition but limited control over the full compute stack. Nvidia remains the default answer for most large-scale AI deployments, and the software gravity around CUDA is not going away just because policymakers would prefer more sovereignty.
Semidynamics is, therefore, trying to find an opening, not replacing the whole AI stack overnight, but attacking inference economics where memory capacity, memory bandwidth, power, and utilization are painful.
What do we think?
AI inference is no longer just about how much matrix math can be placed on a die, and memory architecture is a credible battleground. Challengers rarely win by matching the incumbent spec for spec. They need to change the basis of comparison. Semidynamics is trying to do that by saying: Do not ask only how many TOPS the rack has; ask how much of that compute is usable when the model and context window are large.
The LPDDR angle is neat because it reframes a perceived weakness as a system design choice. HBM has enormous bandwidth, but it is expensive, capacity-limited compared with commodity DRAM options, and tied to advanced packaging constraints. LPDDR offers capacity and cost advantages, but it does not magically solve bandwidth or latency. Semidynamics’ claim is that Gazzillion can hide enough of that latency and manage enough concurrency to make the trade-off favorable for inference.
The new rack details help the company’s case because they show a more complete system vision. The CPU/XPU tray configuration, scale-up and scale-out switching, liquid-cooling manifold, and CDU all indicate that Semidynamics understands the product is not the chip. The product is the rack.
The mid-2028 availability date gives Semidynamics room to execute, but it puts the company into a future competitive landscape that will not stand still. Semidynamics has chosen a difficult but credible wedge. It is not trying to out-Nvidia Nvidia on exactly the same terms. It is arguing that inference has different bottlenecks from training and that the market’s obsession with peak compute is hiding a utilization problem. That is a ball that quite a few system buyers will at least want to try kicking around.
Semidynamics is one of the 151 companies we are following in our AI Processor Tracking Service, which details 292 AIPs. It’s a crazy crowded field, and soon there will be some fallout. Stick with us to get first indications and inside stories on this incredibly dynamic and exciting market. Take a look at our AI library, where, among things, we keep track of the 151 companies offering 292 AI processors. JPR puts the “I” in AI (and because you will ask—Intelligence, market intelligence).
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