Andes Technology has shut down Condor Computing. Condor had been intended to push Andes into data-center-class RISC-V with an RVA23-based licensable core built around an unconventional time-based scheduling architecture. The IP now returns to Andes. The closure is a setback for Andes’ high-end ambitions and for RISC-V’s effort to establish credible alternatives to Arm and x86 in the data center.
In our most recent RISC-V quarterly update, we reported that we understood Andes had cut Condor, its Austin, Texas, high-end design center, back to a skeleton crew, with a future intention perhaps to fold the IP back into the parent company. That has now come to pass, and Condor is no more. CEO Ty Garibay has moved to become vice president of SoC Design at Ambiq, which we wrote about here and here. Garibay is also an adviser at Baya Systems, and at Neurophos, whose CEO we interviewed here.
You can find more context on Andes’ strategy in our interview with the exec team here.
We understand the move follows disappointment in the delivery of Condor’s Cuzco out-of-order CPU, which underperformed targets and had ongoing production issues. This is a blow for RISC-V’s RVA23 profile, on which Condor was based and could potentially have been a flag bearer.
As Andes Technology is currently in a quiet period, they told us they were unable to disclose specific commercial details or financial statuses at this time. However, they did provide the following official statement:
“While we remain committed to our long-term vision on broader computing, we align our organization to best serve the current market momentum on AI, automotive and embedded systems. All Condor IP’s [sic] have been brought back to Andes for further development, and we continue to work with key Condor personnel.”
What was Condor?
Condor Computing Corporation was established in March 2023 as a wholly owned R&D subsidiary of Andes Technology, the Taiwanese RISC-V CPU IP company. Its brief was to build data-center-class RISC-V processor cores entirely in the United States, aligning with the geopolitical imperative of the time.
Andes wanted a US-based engineering pipeline for its most ambitious work, and it judged RISC-V’s high-performance frontier to be where the opening lay. Andes placed the operation in Austin, a growing center of gravity for CPU design, and handed the reins to microprocessor veteran Ty Garibay. Over three decades, Garibay had worked on microprocessors at Motorola, Cyrix, MIPS, Alchemy and Arm; run Arm’s Texas design center and led engineering for Texas Instruments’ OMAP line; held IC design leadership roles at Altera and Intel; served as CTO of Arteris IP; and, at Mythic, led development of a pioneering neural network accelerator.
For most of its history, RISC-V has thrived in the low-power embedded world and has barely troubled Arm or x86 at the top end. Condor was created to change that, chasing performance in the range of 15 to 20 SPECint and beyond. That would put a licensable RISC-V core in the frame for data center work.
By 2025, there was a core to show for it: Cuzco. Cuzco is a wide out-of-order design with a modern branch predictor, a 256-entry reorder buffer and eight execution pipelines. Its distinguishing trick is time-based scheduling. Rather than repeatedly scanning the reorder buffer for instructions whose operands have become ready, the core works out in advance when execution resources will free up and schedules against that, with most of the back-end scheduling handled statically to trim power and complexity. Execution resources are grouped into slices, each a self-contained pair of pipelines able to run any supported instruction. The design is straightforward to scale by adding slices.
None of this is visible to software. Cuzco ran standard RISC-V code and targeted the RVA23 profile, the first RISC-V application profile aimed at high-performance computing. We considered Cuzco in the same general class as SiFive’s P870 and Ventana’s Veyron V1 (now also dead), and a clear step above RISC-V cores already in silicon.
Like Arm and SiFive, Condor was an IP play. For a company building data center or edge-AI silicon, that means acquiring a high-performance CPU without the cost and time of designing one, and without committing to x86 or proprietary Arm licensing terms, but it also means needing to create a working chip.
In July 2025, Condor completed full hardware emulation of the core and booted Linux and other operating systems on it. The following month, it presented Cuzco publicly for the first time, in an architecture session at the Hot Chips symposium. First, customer availability was slated for the fourth quarter of 2025. By early 2026, there had yet to be a final deliverable, and the team was cut from 50, to around 15, tasked with completion of the processor IP, after which the team was disbanded, with some folded back into Andes.
What do we think?
As we said in our last quarterly update, the AI data center is now very much in play for RISC-V (see the full analysis here). Was three years really long enough for Andes to decide that its high-end strategy was bad? We don’t think so. Rather, we suspect the strategy was/is good, but the end results were not up to spec and a key customer remained elusive.
Andes does now have a new and patented microarchitecture built around deep out-of-order execution and an unconventional approach to instruction scheduling. However, the team was cut from 50, to 15, and now to just a handful who really understand the IP within Andes. There is, we understand, no ongoing test silicon development on Cuzco.
While the Condor IP persists at Andes and may have a future, we think more likely that the Andes team will regroup and look at another way to get into the higher end. One possibility could be further CPU development, or even acquisition of complementary GPU or LPU IP.
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