SiFive has launched its third-generation Performance P570 and P550 processor IP. It is aimed at high-performance yet area- and power-constrained SoCs. The P570 Gen 3 adds vector capability, RVA23 profile compliance, dot-product acceleration, and system-level IP support for secure Linux- and Android-class devices. SiFive is positioning the core not as its top-end datacenter CPU, but as a balanced out-of-order RISC-V processor for consumer, commercial IoT, edge AI, and embedded control systems.
SiFive has announced the Performance P570 Gen 3, along with an updated P550 Gen 3, extending its out-of-order RISC-V CPU IP portfolio for customers building power- and area-sensitive SoCs.
The P570 Gen 3 is the vector-enabled member of the pair, while the P550 Gen 3 is offered for customers who want the same class of efficient out-of-order processor but do not require vector acceleration. SiFive describes the P570 as a 3-wide, 13-stage, fully out-of-order superscalar core with an upgraded 128-bit VLEN vector engine, targeting edge AI, high-end consumer devices, commercial IoT, and embedded controller roles inside larger SoCs.
John Ronco, SiFive’s SVP of product & GM SiFive UK, described the P570/P550 Gen 3 to us as “an efficient out-of-order processor designed for great performance per square millimeter and great performance per milliwatt,” rather than as SiFive’s highest-performance CPU. “It’s really designed at that balanced performance point,” he said.
SiFive says the new core delivers a 7–13% gain in traditional CPU workloads across SpecInt 2006–2017, while reducing dynamic power by 13% compared to the earlier P550 Gen 1. For AI-relevant CPU workloads, the company claims the vector pipeline delivers a 2× Geekbench uplift and as much as a 21× improvement in selected AI workloads versus Gen 1, thanks to specialized dot-product instructions for convolution and matrix-multiply operations.
This is not SiFive’s biggest core. Ronco contrasted the P570/P550 Gen 3 family with SiFive’s higher-performance CPUs designed for infrastructure and datacenter use. The new cores are instead aimed at the more balanced part of the market, where area, power, software compatibility, and adequate performance all matter.
The P570 Gen 3 is also notable for supporting the RVA23 application profile. SiFive argues that RVA23 has become a key baseline for Linux-based RISC-V systems, with major software ecosystem players looking to it as a stable target for application-class devices. The profile includes modern features such as vectors, hypervisor support, and security capabilities. SiFive says the P570 implements all mandatory RVA23 extensions and several optional ones.
Beyond the core, SiFive is emphasizing the surrounding subsystem. The company says the P570 Gen 3 is available with a RISC-V-standard-compliant Advanced Interrupt Architecture, WorldGuard security support for trusted execution environments, a second-generation RISC-V-standard-compliant IOMMU (input-output memory management unity), and scalability up to 16 coherent cores in a compute subsystem.
The company has also added optional extensions for security, management, FP16 and BF16 support, vector crypto, and enhanced protected memory. SiFive highlighted dot-product vector extensions, BF16 support, vector crypto extensions, and control-flow integrity-related features such as landing pads and shadow stacks.
SiFive says the P570 is available now and is working with customers across several market segments. For customers with very strict area constraints who do not require vectors, the updated P550 Gen 3 provides an RVA23-compatible alternative.
What do we think?
This launch addresses one of RISC-V’s recurring problems: architectural flexibility is attractive until you need a stable software target.
RISC-V has never lacked optionality. Often it has had too much. Picking and choosing extensions works well for deeply embedded designs. It becomes a liability when the goal is Linux distributions, Android-class devices, commercial developer tools, and security stacks that need a predictable baseline. SiFive’s emphasis on RVA23 standard is the commercial argument for this product.
The P570 Gen 3 sits in the high-volume middle of the market: not a microcontroller, not SiFive’s largest infrastructure CPU, but a core that could credibly live inside a smart TV, wearable, edge AI endpoint, industrial gateway, or heterogeneous consumer SoC. As we have said before, the biggest near-term RISC-V opportunity is probably not beating Arm everywhere, or even anywhere: it is becoming good enough, standard enough, and efficient enough in enough places that SoC teams can adopt it without feeling they are running an experiment.
The vector story is well-judged. SiFive is not claiming the P570 displaces a serious NPU. The argument is narrower: many edge AI and signal-processing workloads benefit from vector acceleration, dot-product operations, and BF16/FP16 support without requiring a dedicated accelerator. The 21× headline figure is workload-specific and should be read as such, but the underlying point is that scalar CPU performance is no longer the only useful measure of an application processor.
SiFive’s decision to develop the dot-product extension and donate it to RISC-V International for standardization is notable. The ecosystem needs both innovation and convergence; moving faster than the standard and then pushing useful work back into it is a sensible strategy for SiFive.
SoC teams are not buying a CPU core; they are buying a platform. Interrupt architecture, IOMMU, security partitioning, coherent clustering, debug and trace: these are table stakes when the alternative is ARM’s mature platform machinery or the internal CPU programs of large semiconductor companies.
RISC-V announcements have a history of saying they’ve hit an inflection point before the ecosystem has caught up. P570 Gen 3 will still need silicon, production boards, and software support to prove commercial traction. However, the elements SiFive is emphasizing — RVA23, vectors, security, IOMMU, performance per watt — are the right ones for the next phase of RISC-V adoption.