Q.ANT CEO Michael Förtsch argues that photonic computing is ready for practical deployment as a coprocessor. The company’s NPU is designed to sit on PCI Express and work alongside CPUs and GPUs, targeting nonlinear functions and data-reduction algorithms where CMOS is less efficient. Förtsch says Q.ANT already has commercial HPC deployments, cloud access through IONOS, and a roadmap built around faster processors, richer software support, and broader developer adoption. He says that photonic computing may occupy the practical middle ground between today’s GPU-dominated AI infrastructure and the promise of quantum computing.
Q.ANT CEO Michael Förtsch (Source: Q.ANT)
Q.ANT stands out in the photonic-computing field because it actually has systems deployed. We spoke to CEO Michael Förtsch at ISC HP 2026 where he explained why Q.ANT sees its photonic NPU as a coprocessor for CPUs and GPUs, why nonlinear functions are the company’s architectural focus, and why photonic computing is closer to practical adoption than quantum computing.
Where does Q.ANT’s photonic processor sit in the compute stack today?
Michael Förtsch: For the moment, we see ourselves as a coprocessor, side-assisting the GPU and the CPU. The workloads we are focused on are the more complex ones—nonlinear functions, for example—because that is where CMOS starts to fall short.
To make that work in real systems, we deliberately built our processors around the PCI Express interface. From an integration point of view, the goal has always been that there should be no difference. We know we are light-based, and most processors today are not, but from the outside-in perspective, the user should not feel that difference.
You look at the Lenovo boards we have here: They ship into data centers in exactly that style. You have PCI slots, you plug our system in, and that is it. We handle the hardware and software integration so that, from the user’s perspective, the only real difference is the acceleration.
Figure 1. Q.ANT and Lenovo Photonic Computing System. (Source: JPR)
When you act as a coprocessor, how do you manage movement between the GPU’s digital realm and your photonic realm?
Förtsch: It depends on the application. What we are showing at the conference is a diffusion model running end to end on our NPU. There is no GPU involved. Memory management is handled by the host CPU, but everything else runs on the NPU card.
That is one extreme. Back at headquarters, we also operate systems where GPUs are co-integrated into the same architecture. In those cases, we decide where each part of the workload is best positioned. For example, we recently ran an image-classifier demo in which the more matmul-heavy workloads were directed toward the GPU, while the nonlinear parts ran on the NPU. The result showed a path toward both performance improvement and energy reduction.
So it is not simply A or B. You have to look at the application and find the temporary optimum. Tomorrow, depending on the algorithm, the right split may be different.
One thing we are proud of is a compiler demonstration we did with Daisytuner. With that compiler, we could take PyTorch code and map it directly onto our system without rewriting the original code. The compiler translated the source code directly into NPU language.
What is Q.ANT’s architectural bet?
Förtsch: When we look at the compute ecosystem, the real problem today is not energy. Energy is the consequence. The real problem is that we use too much data, and the amount of data is defined by the functions we use.
In the past, it did not make much sense to integrate more complex functions to reduce data, because whatever you saved in data movement and energy, you spent on transistors to build the more complex function. It was a one-to-one trade-off.
Our differentiator is that we are not building a vector-matrix machine. We are focused on making complex nonlinear functions nearly as cheap as linear functions. That means we are not walking down the same path as a GPU. GPUs are fantastic. I am always shocked when I see the numbers; they are insane. So why compete with GPUs on their home ground? But we also have to acknowledge that GPUs have limitations. They are not the right architecture for everything. By focusing on nonlinear functions, we can enable algorithms that need a fraction of the data. That is the biggest lever for reducing energy consumption across the stack.
Can you give an example?
Förtsch: In image generation, we have demonstrated the use of a Kolmogorov-Arnold Network (KAN). The mathematics are beautiful and complex, but the important point is that the function set can reduce the amount of data by a factor of 50. The processor then needs to execute Fourier formulas efficiently. With our NPU, those Fourier formulas are essentially as easy to build as a linear function. In that case, we start trading 50 to 1.
For a more moderate example, take image classification. ResNet-50 is a standard problem: convolution layer on convolution layer. You can replace that with a smarter algorithm that reduces the data by a factor of 6 to 8. The requirement is that the processor can run a Fourier transformation efficiently. If that transformation gives you an energy advantage, you save on the die and you save on memory movement. And the best bit, in my opinion, is the bit that was never sent—the bit we did not need to model the problem in the first place.
That is where we see our competitive edge. We are not trying to beat the CPU or the GPU. For extensive vector-matrix multiplication, I would still vote for the GPU today. The provocative question is, Why does everything we do have to be vector-matrix multiplication? Today’s answer is, because we do not have anything better.
One of the notable differences between Q.ANT and other companies in this space is that you actually have deployments. How commercial are those deployments?
Förtsch: On one side, we have HPC centers in Europe as customers. They commercially source systems from us and offer them to the scientific community to develop new applications. At the same time, we have been approached by more than 100 industrial clients asking whether they can test our systems with real workloads. The challenge is that we are not a data center, and it does not make sense for us to become one. That is why we partnered with IONOS this year on the European side. It made our service rentable through the cloud—and we are booked.
What does the roadmap look like? What is the next big problem you need to solve?
Förtsch: With ISC, I think we stepped out of the ‘playing around’ phase and into the zone where we address modern algorithms, such as diffusion models, that are genuinely relevant to today’s compute problems.
The next task is to increase the performance of the full processor stack. Internally, we have set a benchmark that every year we want to bring a new processor to market that outperforms its predecessor by at least a factor of 10, and ideally by a factor of 100. We will do that by offering more and more functions as primitives on the die, while also growing the software ecosystem. From the customer’s perspective, using our system through PyTorch should feel as natural as using a GPU underneath. There should not be a difference in how they code.
The larger challenge is adoption. In my words, we have created a new chicken. Now our customers have to produce eggs. These systems can do wonderful things, but the world has to be educated on what they can do, and the technology has to be made available to a larger community of developers. We have crossed into a productivity zone, where customers can already start gaining performance benefits. Now we need to widen the ecosystem and bring in as many co-developers as possible.
How does Q.ANT scale performance physically? Can you add more chips in parallel, or increase the size of the photonic chip?
Förtsch: Photonics does not scale through miniaturization in the same way CMOS does. The components do not work that way.
We see three main degrees of freedom. The first is the physical layer. Today, we still operate on a single die, but we could use multiple dies optically connected. We can also increase the clock rate. Optically, going to 10 GHz and above is not the problem; the material allows it. The question is whether we can drive it. The second physical knob is wavelength. One channel with one wavelength is one channel. One channel with four wavelengths gives you a factor of four without adding much else. Then there is the arithmetic layer: adding more dedicated elements for functions such as Fourier transformation and convolution. That means enriching the set of one-shot photonic function elements and thinking about how multiple chips with different functions cooperate. Finally, there is the algorithm layer. Mathematicians have spent decades thinking about how to reduce the amount of data needed to describe a problem. Many of those algorithms were underused because they did not map well onto CMOS. If those fundamental functions become primitives, it can boost the whole ecosystem.
You manufacture by yourselves today. Do you intend to keep owning that?
Förtsch: When we started, we thought we would become a fabless company. Obviously, we are not fabless today. We have a pilot line. The reason was simple: We had to demonstrate the technology. We had to show the world once that this could work. Looking forward, we will scale this business in whatever way helps make the technology a standard. If that means building fabs, then we have to consider it. But these fabs are not as expensive as leading-edge CMOS fabs. What we have demonstrated is that we can reuse a legacy 1990s fab at a 90 nm node. We may even be able to go above that, to 355 nm i-line stepper systems. That is not comparable to building a 3 nm EUV fab. At the same time, the pilot line is extremely valuable for R&D because it gives us development speed. Every three months, a new chip.
For commercialization, we are looking for partners willing to license our PDK and IP, and manufacture our class of chips. We did the development work and de-risked the concept by demonstrating a processor application. Now we are opening the business model to R&D and manufacturing partners.
A 90 nm node is not fashionable anymore, but we can say, Let’s team up, and you benefit, and we benefit. The reason is speed. The faster we scale into the market, the more likely it is that we help solve the problem that is stopping AI from scaling everywhere.
Figure 2. Q.ANT Photonic NPU PCI-Express board. (Source: JPR)
What should I ask you, if I was smarter?
Förtsch: The question is: How do we help the world understand this? When you walk around here, people still talk a lot about quantum. I am not against quantum, but I think the industry started talking too early about the possibilities of quantum processors. With photonic computing, I feel the opposite has happened. Systems are already deployed, but the community does not talk about them enough.
The question we should ask is, How do we educate the world about the benefits photonic computing can bring without requiring anyone to integrate a quantum computer into their stack? Our system comes through a PCI Express port. That is a much easier lift, but still a significant one.
When we talk to people who are less deeply educated in computing, they often say, ‘We have GPUs today, and the next supercomputer will be quantum.’ We have to say, ‘Wait a second, it is not like that. There is something between those worlds that is already practical.’
Most people recognize that quantum is still several years away, but there is also crossover interest in photonic quantum. People seem open to the idea that some form of photonic solution is part of the future. The tricky part is that many companies are heavily invested in GPUs and GPU-like products. Nobody wants the market to move too fast, because they still need to extract value from what they have built. Even if they believe in photonics, the question is when and how to support the transition.
Förtsch: That is right. We already see an ecosystem shift, and the timing is interesting.
In 2024, when we first came out publicly with photonic computing, it was after Lightmatter had not succeeded in building its first processor. We were at a Silicon Valley conference, and people from Nvidia made the generic statement that photonics would never make it into the compute stack. They said it would be copper, copper, copper. One year later, Nvidia announced that Rubin would use advanced optical packaging. So they had to know about photonics.
Maybe it is a positive sign. If Nvidia is not talking about photonic computing publicly, perhaps they are working on it more than we think.
Wrong-footing the market is a skill.
Förtsch: That is true.
What do we think?
Compared with Neurophos and Lumai, Q.ANT’s headline performance claims are relatively restrained, but Q.ANT’s differentiation is that it is already in the market. Its systems are deployed as PCIe-based coprocessors in real HPC environments, including LRZ, and the company is talking about grown-up things like customer adoption, compiler support, cloud access, and production constraints.
Neurophos and Lumai are more directly chasing the AI accelerator prize, with optical approaches aimed at the matrix-heavy workloads that dominate today’s LLM infrastructure. Q.ANT is making a narrower bet: that photonics can create an advantage where CMOS is weakest, particularly in nonlinear functions, Fourier transforms, and algorithms that reduce the amount of data moved through the system. That is less sexy than “replace the GPU,” but it is also more defensible. Michael Förtsch’s argument is essentially that the best bit is the bit never sent—a useful provocation in an industry still trying to brute-force AI scaling with more memory and more GPUs.
Q.ANT is not a GPU killer, but it is an early proof point for heterogeneous photonic acceleration: Its market credibility is high because customers can touch the hardware.
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