Flex Logix Technologies built two things: an eFPGA IP business with real customers, and an edge AI inference chip that applied that same interconnect expertise to neural network acceleration. The InferX X1—four nnMAX tiles, 8.4 TOPS, TSMC 16 nm, $399 PCIe card—shipped in 2021 and found real buyers. Analog Devices acquired the company in November 2024. The nnMAX architecture is technically differentiated, and the IP licensing model continues under ADI. For edge inference ISVs and silicon teams, the story isn’t over.
Geoffrey Tate knows how to build semiconductor companies. He was founding CEO of Rambus, the memory interface IP company that generated substantial royalties and substantial controversy in equal measure. In 2014, he co-founded Flex Logix Technologies in Mountain View, California, with Cheng C. Wang—who came from Broadcom and holds a PhD in electrical engineering from UCLA—and Dejan Markovic, a UCLA professor specializing in VLSI design. Wang served as SVP of Engineering and Software. The three brought complementary backgrounds: Tate on business and strategy, Wang on architecture and implementation, Markovic on academic research and novel circuit design.
The founding insight was an interconnect observation. FPGA performance and power are dominated by routing—moving data between logic tiles burns more energy than the computation itself. Flex Logix had developed a patented interconnect fabric (ArrayLinx, RAMLinx, XFLX) that reduced routing area to five to seven metal layers instead of the 10 to 12 that conventional FPGA routing requires. They built the eFPGA IP business on that foundation, licensing the EFLX eFPGA cores to SoC designers at companies including MorningCore/Datang Telecom, DARPA, Boeing, Harvard, Sandia, and SiFive. TSMC named them a founding eFPGA IP Alliance Partner.
Then Wang realized the same interconnect architecture that made eFPGA routing efficient could make neural network inference efficient—specifically, it could solve the DRAM bandwidth problem that limits edge AI performance. The nnMAX tile was born from that insight.
The InferX X1 architecture
Each nnMAX tile contains 1,024 MAC units organized in clusters of 64, with weights stored locally in L0 SRAM. The MACs run at 1.067 GHz. Each tile connects to 1, 2, or 4 MB of on-chip SRAM, depending on configuration. ArrayLinx performs the interconnect remapping between tiles at runtime—reconfiguring thousands of wiring connections between layers in approximately 1 μs using partial reconfiguration, without any GDS change. This is the key efficiency mechanism: intermediate activations stay in SRAM rather than going out to DRAM and coming back.
The InferX X1 chip arrays four nnMAX tiles in a 2×2 configuration plus a 1×1 EFLX eFPGA block. Each tile delivers approximately 2.1 TOPS on TSMC 16 nm, giving the X1 8.4 TOPS total. The chip requires only a single DRAM—a direct consequence of high MAC utilization and the SRAM-centric architecture. The nnMAX architecture scales to N×N tile arrays without any GDS modification, targeting up to 100-plus TOPS for larger implementations or IP customers that want to integrate nnMAX into their own SoCs.
Figure 1. Block diagram Flex Logix’s InferX XI chip. (Source: JPR)
No official Flex Logix block diagram was publicly released—they kept the internal microarchitecture under NDA. This is constructed from the EEJournal technical write-up, SemiWiki coverage, and Flex Logix’s own launch press release.
Host interface is PCIe Gen3/4 x4. DRAM is 32-bit LPDDR4x. Precision: INT8, INT16, and BF16, with mixed precision supported within a single network. The nnMAX Compiler ingests TensorFlow Lite or ONNX models and maps them to the tile architecture, hiding the internal interconnect configuration from the user entirely. Frameworks don’t see ArrayLinx—they see a standard inference runtime.
Flex Logix announced the InferX X1 at the Linley Processor Conference in April 2019. Production availability came in November 2021—a two-year development cycle that stretched through COVID. The X1P1 PCIe half-height, half-length card launched at $399. In March 2022, Flex Logix announced production availability of InferX X1m boards targeting edge AI vision systems. The company also offered the X1 as a stand-alone chip for embedded designs.
Revenue estimates run $4.5M annually per Kona Equity modest for a company that raised $82M, but consistent with an early-stage chip company still in initial deployment cycles at acquisition. At 32–52 employees (sources vary by date), the revenue-per-employee figure was below industry average, which is typical for IP-plus-silicon companies still in commercial ramp.
Funding and acquisition
Flex Logix raised $82M across four rounds from five investors. The Series D in March 2021 was $55M, led by Mithril Capital with participation from Lux Capital and Eclipse. Prior rounds totaled approximately $27M. Analog Devices acquired the company on November 11, 2024. Financial terms were not disclosed.
ADI’s strategic rationale is clear: The nnMAX IP core provides a scalable inference accelerator block that ADI can embed in its own signal processing SoCs, and the EFLX eFPGA IP adds reconfigurability to ADI’s industrial and communications portfolio. Flex Logix had already demonstrated nnMAX on both TSMC 16 nm and GlobalFoundries 12LP under a US government agreement—giving the IP multi-foundry portability that matters for defense and aerospace customers.
Table 1. Flex Logix overview.
Flex Logix solved a real architectural problem—DRAM bandwidth as the binding constraint on edge inference—with a solution derived from a decade of eFPGA interconnect expertise. The nnMAX tile architecture is genuinely differentiated: NxN scalability without GDS changes, sub-microsecond partial reconfiguration between layers, and the ability to keep intermediate data in SRAM at a level that single-DRAM operation becomes practical. ADI’s acquisition removes the stand-alone-company risk and provides the IP with a distribution channel through ADI’s SoC and module portfolio. For ISVs and silicon teams evaluating inference IP, nnMAX under ADI is worth tracking—the architecture survived acquisition, which is the filter that matters.
What do we think?
Flex Logix got the architecture right—the interconnect-derived approach to keeping inference on-chip is a real efficiency gain, not a benchmark artifact. The $399 PCIe card at 8.4 TOPS was competitively positioned for 2021 edge deployments. The revenue trajectory didn’t justify the $82M raised as a stand-alone company, but ADI didn’t buy the revenue. They bought the IP and the team. For AI inference IP embedded in industrial SoCs, that’s a reasonable acquisition thesis.
Flex Logix’s nnMAX architecture marks an inflection point in how AI inference IP gets built: the recognition that FPGA-style programmable interconnect—historically dismissed as too area-expensive for AI accelerators—can be the mechanism that eliminates the DRAM bandwidth problem entirely. That inflection point is now visible across the industry as architects revisit routing topology for AI dataflows rather than defaulting to systolic arrays. ADI’s acquisition confirms that major analog IC companies see embedded inference IP as a core SoC capability, not an optional block—which is its own inflection point in how the analog semiconductor industry approaches AI.
ADI has product availability for anyone evaluating edge inference hardware. The $399 PCIe card entry point, the ADI acquisition context confirming long-term IP continuity, and the eFPGA customer list as a signal that Flex Logix’s technology found real industrial buyers before the acquisition.
The ADI Flex Logix InferX XI chip is one of the 152 AI processors in our AI Processor Tracking Service, which also lists performance and other specifications for 291 products. And if you’re interested in FPGAs, we have a report on that too.
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