Infineon’s new AURIX RC1 automotive microcontroller platform marks a major RISC-V design win for MIPS and GlobalFoundries. With MIPS processor IP at its core, RC1 demonstrates how RISC-V is moving into safety-critical automotive computing and supports GF’s ambition to build a billion-dollar IP, software, and custom silicon business. It also raises the question: Could RISC-V eventually replace Infineon’s proprietary TriCore architecture?
(Source: Infineon)
Infineon has announced AURIX RC1, a new RISC-V-based automotive microcontroller platform designed for software-defined vehicles, industrial systems, and physical AI applications. The announcement is a significant expansion of RISC-V into one of the automotive industry’s most demanding semiconductor markets and a major design win for MIPS, now part of GlobalFoundries (GF).
Although Infineon’s November 4 announcement did not identify its CPU IP supplier, Thomas Boehm, senior vice president and general manager of Automotive Microcontrollers at Infineon, confirmed in an interview with EE Times Japan that AURIX RC1 uses MIPS processor IP.
Boehm said Infineon and MIPS had an established working relationship and that access to a strong development partner was an important consideration. MIPS’ ability to provide RISC-V cores across multiple performance classes, from security and real-time control to 64-bit computing, and its ability to meet Infineon’s development schedule were important factors in the selection. It is also worth noting the investment MIPS has put into relevant ASIL safety certifications.
AURIX RC1 is Infineon’s first RISC-V-based microcontroller family. It will provide a common processing architecture spanning applications including powertrain, chassis, battery management, body electronics, zonal controllers, and safety management for advanced driver assistance systems.
Figure 1. MIPS RISC-V processors populate every sector of next-gen Avs. (Source: Infineon)
Unveiled ahead of electronica 2026 in Munich, the family is expected to begin sampling in the first half of 2027.
Depending on the configuration, RC1 devices will integrate up to 12 32-bit processing cores, up to 40 MB of embedded memory, and an advanced parallel processing unit for edge AI workloads. Infineon also plans to extend the family with 64-bit microprocessor capabilities, allowing Linux and other POSIX-based operating systems to run alongside the real-time control environment.
The platform is designed to support automotive functional safety applications up to ASIL D, alongside cybersecurity requirements including ISO/SAE 21434 and emerging post-quantum cryptography. Communications capabilities include CAN XL, 10BASE-T1S, and multi-gigabit Ethernet, with selected devices incorporating Infineon’s Brightlane Ethernet switching technology.
A new DriveCore software ecosystem combines Infineon’s own software with third-party development tools, middleware, AUTOSAR support, and pre-integrated software packages. Virtual prototyping and AI-assisted software migration tools are intended to help customers transition existing applications from AURIX and Traveo devices.
Peter Schiefer, president of Infineon’s Automotive Division, said: “Delivering vehicles and other physical systems that become smarter, safer, and more efficient over time through new software fundamentally changes the requirements for the computing hardware. Microcontrollers need to become more configurable, scalable, and adaptable, while maintaining highest safety and security levels as applications evolve.”
From Quintauris to AURIX RC1
Although RC1 is Infineon’s first announced RISC-V MCU platform, the direction is not unexpected.
Infineon announced plans for an automotive RISC-V microcontroller family in March 2025 and has been a central participant in Quintauris, the joint venture established in December 2023 by Bosch, Infineon, Nordic Semiconductor, NXP, and Qualcomm. STMicroelectronics subsequently joined the initiative.
Quintauris was established to accelerate RISC-V adoption through common specifications, reference architectures, and interoperable software environments, initially concentrating on automotive applications.
In November 2025, Quintauris released RT-Europa, a reference platform for automotive real-time processors. It addresses requirements extending beyond the RISC-V instruction set, including deterministic execution, memory protection, interrupt handling, system integration, software compatibility, and verification.
In December 2025, Quintauris announced a strategic collaboration with MIPS to integrate its Atlas portfolio of RISC-V processor IP into RT-Europa and future embedded platforms. The initiative was intended to help bring commercially proven processor technology into an interoperable automotive environment.
Quintauris has also established relationships with other IP suppliers, including Synopsys, Andes Technology, and Nuclei, as well as automotive software specialists.
At CES 2026, Quintauris demonstrated its RT-Europa software reference architecture on an Infineon RC1 prototype, providing an early indication of the relationship between the consortium’s platform work and Infineon’s future products.
The latest announcement takes that work a substantial step further, putting commercial RISC-V IP at the center of a major automotive semiconductor supplier’s next-generation product family.
Why do we think?
This is an important announcement for RISC-V, but perhaps an even bigger one for MIPS and GlobalFoundries.
Infineon’s participation in Quintauris has largely been leading towards something like this. The consortium was never about promoting an open instruction set. It was about solving the problem of making RISC-V practical for automotive manufacturers that need functional safety, software compatibility, and products supported for many years.
RC1 is one of the first substantial outcomes of that strategy from a founding member. The choice of MIPS is particularly interesting given its own involvement in Quintauris and its established relationship with Infineon.
We have previously noted that the acquisition of MIPS in 2025, followed by the addition of Synopsys’ ARC processor IP business in June 2026, was transforming GlobalFoundries from a manufacturer that supported RISC-V into a company that owned an increasingly substantial part of the RISC-V technology stack. When GF acquired MIPS, it gained a processor IP business with experience in real-time, safety-critical, and domain-specific computing. Adding ARC brought more processor IP, engineering resources, AI capabilities, and software development tools, including ASIP Designer and ASIP Programmer. We understand that the team is continuing to innovate, especially in the AI capabilities. The resulting business can offer customers considerably more than a RISC-V CPU core. It has both the processor IP and access to manufacturing needed to help customers build complete silicon products.
GF has considerably bigger ambitions for MIPS than simply growing its licensing revenue. At its May 2026 Investor Day, GF CEO Tim Breen set a target of approximately $1 billion in annual revenue by 2030 from its IP, software, and custom silicon activities. It is an ambitious target, particularly given that MIPS was acquired only in August 2025. The strategy is to move beyond traditional IP licensing and royalties into software and custom silicon, where GF can capture more of the value of a completed chip.
An important part of this is the expansion of MIPS’ silicon design capabilities. GF has increased MIP’s engineering resources by several hundred people through the ARC acquisition and is building a broader team capable of developing complete silicon platforms. This creates the potential for MIPS to undertake chip design projects for GF customers, using its own processor technology and other licensed IP, with manufacturing handled by GF.
We think this team expansion will continue inorganically. Today, MIPS shares space with Tenstorrent in Silicon Valley, and Tenstorrent would certainly fill a gap in the portfolio, although we’d anticipate a potential bidding war with Intel and Qualcomm if GF made that move. Imagination Technologies has a significant history with MIPS too and would be a natural addition to GF’s IP library. Imagination recently repaid its loan from Fortress in a move interpreted by some as preparation for a sale.
There is another strategic possibility: MIPS developing and selling its own branded commercial silicon, rather than limiting itself to licensing IP or designing chips for others. GF has not announced such a product strategy, but the design resources and technology portfolio make it feasible. That would be a significant change to the MIPS business model, positioning it as both an IP supplier and potentially a semiconductor product company, backed by one of the industry’s major foundries. For an IP company, selling silicon is fraught, as we have seen with Arm, and it may be complex for GF to position such a move too. More straightforward is to offer custom silicon development for foundry customers.
We don’t yet know that the Infineon RC1 devices will themselves be manufactured by GF. Licensing MIPS IP does not establish where Infineon intends to fabricate the chips. Nevertheless, the design win strengthens the credibility of the broader GF/MIPS proposition.
There is a connection to Infineon’s existing silicon. Its TriCore-based AURIX TC4x devices already use Synopsys ARC EV processor IP in their parallel processing unit for AI acceleration. That IP business is now also part of GF/MIPS, giving the combined company relationships and technology already established within Infineon’s automotive product portfolio.
Infineon explicitly positions RISC-V as a third architectural pillar alongside TriCore and Arm. Going forward, the AURIX brand will encompass both TriCore- and RISC-V-based devices, while Traveo and PSoC continue to use Arm. Together, these architectures cover everything from entry-level controllers to high-performance centralized computing.
But three is a lot of processor architectures to maintain, particularly when each brings its own software and verification requirements. If RISC-V can eventually cover the applications currently served by both TriCore and Arm, does Infineon really need all three in the long term? Infineon has made no announcement about replacing TriCore, and existing AURIX products will need support for many years. Nevertheless, we wonder whether the longer-term plan is to move the AURIX portfolio entirely to RISC-V. That would represent a serious endorsement of the architecture’s maturity and commercial future.
This announcement aligns with the central argument of our latest RISC-V Market Insights report: Commercial value is moving beyond the instruction set architecture. The report highlighted growing Tier 1 involvement in RISC-V, including Qualcomm’s disclosed long-term roadmap, and argued that the commercial opportunity increasingly lies in complete, supported computing platforms rather than processor cores alone.
RISC-V provides a common architectural foundation and greater flexibility over future development for Infineon. Quintauris helps establish the specifications and ecosystem needed to make it practical. MIPS supplies commercial processor IP and development expertise. Infineon then combines those elements with its automotive experience, safety capabilities, peripherals, software, and customer relationships to deliver a differentiated product.
RISC-V does not necessarily eliminate the role of commercial IP suppliers. Indeed, by lowering barriers around the ISA itself, it may create greater opportunities for companies capable of delivering the rest of the technology and development stack. That is precisely what GF is trying to build around MIPS.
RC1 silicon samples are not expected until 2027, and automotive design cycles mean the commercial impact will take time to emerge. Nevertheless, this is a substantial design win for MIPS, and potentially an important milestone in GF’s efforts to build a billion-dollar business.
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